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Job Title:

Hardware Engineer - Santa Clara, CA

Job Description:

Our Client is a privately held fabless semiconductor corporation based in Santa Clara, California. They design high-performance, low-power FPGAs using advanced process node technologies.
Members of our team participate in all phases of the FPGA product-development cycle, from architecture conception to circuit design and implementation to high-volume manufacturing. New employees will have the opportunity to contribute to all of these phases and work with the world’s most advanced process technology.

Position Profile Name: Hardware Engineer – Circuit Design
Type of Position: Regular, Exempt
Location: Santa Clara, CA

Job Description and Responsibilities

The employee will work on the design, implementation, and characterization of full-custom, high-performance digital logic in 14nm/16nm and below. The employee will share responsibilities across design and verification. His or her responsibilities will include the following:

• CMOS Circuit design of different macros in the FPGA fabric (full-custom portion of the FPGA), including clock distribution in the fabric.
• Track planning over the fabric, evaluating performance of various metals in the interconnect stack.
• Timing, em, and ir flows and methodologies for the fabric.
• Library characterization of custom standard cell library cells.
• Assist in the physical design of several fabric IPs using industry standard place and route tools (RTL to GDS).
• Collaborate with other members of the team to optimize our physical design and verification methodologies.
• Estimate power, performance, and area of RTL blocks both before and after physical implementation.
• Develop design methodologies and guidelines for each process node.
• Work closely with foundry employees on process development, customer support, EDA, reliability, test, and product qualification.
• Develop automated processes for block-level and system-level verification.

Skills and Qualifications:
• Experience with digital VLSI CMOS circuit design and physical design in advanced FinFet technology nodes.
• Experience with schematic entry, netlist generation, and SPICE simulation.
• Understanding of layout, layout dependent effects, and parasitic effects.
• Comfortable with physical design, verification, and analysis tools from vendors like Synopsys, Ansys.
• Comfortable designing flows and methodologies from scratch and maintaining them.
• Excellent debugging skills.
• Experience reading and writing RTL (e.g., Verilog).
• Experience with commercial ASIC CAD tools (e.g. DC, ICC, PrimeTime, Totem).
• Experience with commercial CAD flows (LVS, DRC, simulation, etc.).
• Comfortable programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g. 5000+ lines of code).
• Familiarity with object-oriented programming concepts is a plus.
• Familiarity with revision-control systems (e.g., perforce, git) is a plus.
• Familiarity with using and/or designing FPGAs is a plus.
• Familiarity with hardware protocols such as Ethernet, PCIe, & DDR3/4 is a plus.
• Well organized, punctual, and excellent communication skills.
• MS in Electrical Engineering with +2-10 years experience.

If you are interested in applying, please email me at: Thomas.Cooper (at), call 408-367-1478, or click the “Apply” button.

Job ID:

Dept ID:

Santa Clara, CA
United States of America

Engineering / Engineering

Job Type:
Direct Hire Position
Folder Group ID

Posted Date:4/3/2019



Apply for this Position

Job Title: Hardware Engineer

Location: Santa Clara, CA

Job Type: Direct Hire Position

Reference ID: 362345

Posted Date: 4/3/2019

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